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| INTEGRATED CIRCUITS PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator Preliminary specification 1999 Mar 01 Philips Semiconductors Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 FEATURES * Mixed 2.5V and 3.3V operation * Four CPU clocks at 2.5V * Eight PCI clocks at 3.3V, one free-running (synchronous with CPU clocks) PIN CONFIGURATION VSS REF0 REF1 VDD3V XTAL_IN XTAL_OUT VSS PCICLK_F PCICLK1 VDD3V PCICLK2 PCICLK3 VSS PCICLK4 PCICLK5 VDD3V PCICLK6 PCICLK7 VSS VSS 3V66_0 3V66_1 VDD3V VSS 3V66_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD25V APIC2 APIC1 APIC0 VSS VDD25V CPUDIV2_1 CPUDIV2_0 VSS VDD25V CPUCLK3 CPUCLK2 VSS VDD25V CPUCLK1 CPUCLK0 VSS VDD3V VSS PCISTOP CPUSTOP PWRDWN SPREAD SEL1 SEL0 VDD3V 48MHz VSS * Four 3.3V fixed clocks @ 66MHz * Two 2.5V CPUDIV2 clocks @ 1/2 CPU clock frequency * Three 2.5V IOAPIC clocks @ 16.67 MHz * One 3.3V 48MHz USB clock * Two 3.3V reference clocks @ 14.318 MHz * Reference 14.31818 MHz Xtal oscillator input * 133 MHz or 100 MHz operation * Power management control input pins * LOW CPU clock jitter 250 ps cycle-cycle * LOW skew outputs * 0.0ns - 1.5ns CPU - 3V66 delay * 1.5ns - 4.0ns 3V66 - PCI delay * 1.5ns - 4.0 ns CPU - IOAPIC delay * Available in 56-pin SSOP package * 0.5% center spread spectrum capability via select pins; -0.5% down spread spectrum capability via select pins DESCRIPTION The PCK2010 is a clock synthesizer/driver chip for a PentiumII and other similar processors. The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2 clock outputs running at 1/2 CPU clock frequency (66MHz or 50MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two 3.3V reference clock outputs at 14.318MHz. All clock outputs meet Intel's drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. 3V66_3 VDD3V SEL133/100 SW00352 ORDERING INFORMATION PACKAGES 56-Pin Plastic SSOP TEMPERATURE RANGE 0C to +70C OUTSIDE NORTH AMERICA PCK2010 DL NORTH AMERICA PCK2010 DL DRAWING NUMBER SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. 2 1999 Mar 01 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 PIN DESCRIPTION PIN NUMBER 2,3 5 6 8 9, 11, 12, 14, 15, 17, 18 21, 22, 25, 26 28 30 32, 33 34 35 36 37 41, 42, 45, 46 49, 50 53, 54, 55 4, 10, 16, 23, 27, 31, 39 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 43, 47, 51, 56 SYMBOL REF [0-1] XTAL_IN XTAL_OUT PCICLK_F PCICLK [1-7] 3V66 [0-3] SEL133/100 48MHz SEL [0-1] SPREAD PWRDWN CPUSTOP PCISTOP CPUCLK [0-3] CPUDIV_2 [0-1] IOAPIC [0-2] VDD3V VSS VDD25V FUNCTION 3.3V 14.318 MHz clock output 14.318 MHz crystal input 14.318 MHz crystal output 3.3V free running PCI clock 3.3V PCI clock outputs 3.3V fixed 66MHz clock outputs Select input pin for enabling 133MHz or 100MHz CPU outputs. H = 133MHz, L = 100MHz 3.3V fixed 48MHZ clock output Logic select pins. TTL levels. 3.3V LVTTL input. Enables spread spectrum mode when held LOW. 3.3V LVTTL input. Device enters powerdown mode when held LOW. 3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2 output remains on all the time. 3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW. 2.5V CPU output. 133MHz or 100MHz depending on state of input pin SEL133/100. 2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz depending on state of input pin SEL133/100. 2.5V clock outputs running divide synchronous with the CPU clock frequency. Fixed 16.67 MHz limit. 3.3V power supply. Ground 2.5V power supply NOTES: 1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5V supply, all remaining VDD pins tied to a common 3.3V supply and all VSS pins being common. 1999 Mar 01 3 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 BLOCK DIAGRAM LOGIC PWRDWN LOGIC XTAL_IN X 14.318 MHZ OSC USBPLL X REF [0-1](14.318 MHz) XTAL_OUT X PWRDWN LOGIC X 48MHz SYSPLL STOP X CPUCLK [0-3] STOP LOGIC X 3V66 [0-3] (66MHz) PWRDWN LOGIC SEL0 X SEL1 X SPREAD X SEL133/100 X PCISTOP X CPUSTOP X STOP PWRDWN LOGIC X CPUDIV2 [0-1] X PCICLK_F (33MHz) X PCICLK [1-7] (33MHz) PWRDWN X PWRDWN LOGIC X APIC [0-2] (1/2 PCI) SW00353 1999 Mar 01 4 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM BACK SIDE SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM FRONT SIDE AVC AVC AVC PCK2509S or PCK2510S The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SDRAM SW00403 FUNCTION TABLE SEL 133/100 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CPU HI-Z N/A 100MHz 100MHz TCLK/2 N/A 133MHz 133MHz CPUDIV2 HI-Z N/A 50MHz 50MHz TCLK/4 N/A 66MHz 66MHz 3V66 HI-Z N/A 66MHz 66MHz TCLK/4 N/A 66MHz 66MHz PCI HI-Z N/A 33MHz 33MHz TCLK/8 N/A 33MHz 33MHz 48MHz HI-Z N/A HI-Z 48MHz TCLK/2 N/A HI-Z 48MHz REF HI-Z N/A 14.318MHz 14.318MHz TCLK N/A 14.318MHz 14.318MHz IOAPIC HI-Z N/A 16.67MHz 16.67MHz TCLK/16 N/A 16.67MHz 16.67MHz NOTES 1 2 3 4, 7, 8 5, 6 2 3 4, 7, 8 NOTES: 1. Required for board level ``bed-of-nails" testing. 2. Used to support Intel confidential application. 3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state. 4. ``Normal" mode of operation. 5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic. 6. Required for DC output impedance verification. 7. Frequency accuracy of 48MHz must be +167 PPM to match USB default. 8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz CLOCK OUTPUT USBCLK7 TARGET FREQUENCY (MHz) 48.0 ACTUAL FREQUENCY (MHz) 48.008 PPM 167 1999 Mar 01 5 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 CLOCK ENABLE CONFIGURATION CPUSTOP X 0 0 1 1 PWRDWN 0 1 1 1 1 PCISTOP X 0 1 0 1 CPUCLK LOW LOW LOW ON ON CPUDIV2 LOW ON ON ON ON APIC LOW ON ON ON ON 3V66 LOW LOW LOW ON ON PCI LOW LOW ON LOW ON PCIF LOW ON ON ON ON REF 48MHz LOW ON ON ON ON OSC OFF ON ON ON ON VCOs OFF ON ON ON ON NOTES: 1. LOW means outputs held static LOW as per latency requirement below 2. ON means active. 3. PWRDWN pulled LOW, impacts all outputs including REF and 48MHz outputs. 4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW. 5. CPUDIV2, IOAPIC, REF, 48MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when PWRDWN is LOW. POWER MANAGEMENT REQUIREMENTS LATENCY SG SIGNAL SG SIGNAL S STATE NO. OF RISING EDGES OF FREE RUNNING PCICLK 1 1 1 1 3ms 2 MAX CPUSTOP 0 (DISABLED) 1 (ENABLED) PCISTOP 0 (DISABLED) 1 (ENABLED) PWRDWN 1 (NORMAL OPERATION) 0 (POWER DOWN) NOTES: 1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the first valid clock that comes out of the device. 2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0V) SYMBOL VDD3 VDDQ3 VDDQ2 IIK VI IOK VO IO TSTG PTOT PARAMETER DC 3.3V core supply voltage DC 3.3V I/O supply voltage DC 2.5V I/O supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range: -40 to +125C above +55C derate linearly with 11.3mW/K VI < 0 Note 2 VO > VCC or VO < 0 Note 2 VO = 0 to VCC -65 -0.5 -0.5 CONDITION LIMITS MIN -0.5 -0.5 -0.5 MAX +4.6 +4.6 +3.6 -50 5.5 50 VCC + 0.5 50 +150 850 UNIT V V V mA V mA V mA C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1999 Mar 01 6 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VDD3V VDD25V PARAMETER DC 3.3V core supply voltage DC 2.5V I/O supply voltage Capacitive load on: CPUCLK PCICLK CPUDIV2 3V66 48MHz clock REF IOAPIC DC input voltage range DC output voltage range Reference frequency, oscillator nominal value Operating ambient temperature range in free air 1 device load, possible 2 loads Must meet PCI 2.1 requirements 1 device load, possible 2 loads 1 device load, possible 2 loads 1 device load 1 device load 1 device load CONDITIONS MIN 3.135 2.375 10 10 10 10 10 10 10 0 0 14.31818 0 MAX 3.465 2.625 20 30 20 30 20 20 20 VDD3V VDD25V VDD3V 14.31818 +70 V V UNIT CL pF VI VO fREF Tamb V V MHz C POWER MANAGEMENT CK133 CONDITION Power-down mode (PWRDWN = 0) Full active 100MHz SEL133/100# = 0 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 Full active 133MHz SEL133/100# = 1 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 MAXIMUM 2.5V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V = 2.625V ALL STATIC INPUTS = VDD3V OR VSS 100A MAXIMUM 3.3V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V= 3.465V ALL STATIC INPUTS = VDD3V OR VSS 200A 75mA 160mA 90mA 160mA 1999 Mar 01 7 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 DC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER VDD (V) VIH VIL VOH2 HIGH level input voltage LOW level input voltage 2.5V output HIGH voltage CPUCLK, IOAPIC, CPUDIV2 2.5V output LOW voltage CPUCLK, IOAPIC, CPUDIV2 3.3V output HIGH voltage REF, 48MHz 3.3V output LOW voltage REF, 48MHz 3.3V output HIGH voltage PCI, 3V66 3.3V output LOW voltage PCI, 3V66 CPUCLK output HIGH current 48MHz, REF output HIGH current PCI, 3V66 output HIGH current CPUCLK output LOW current 48MHz, REF output LOW current PCI, 3V66 output LOW current Input leakage current 3-State output OFF-State current Input pin capacitance Xtal pin capacitance, as seen by external crystal Output pin capacitance O erating su ly Operating supply current Powerdown supply current Idd2 O erating su ly Operating supply current Powerdown supply current 2.625 100MHz mode 3.465 133MHz mode 100MHz mode 133MHz mode Outputs loaded1 Outputs loaded1 Output loaded1 Output loaded1 18 6 160 160 200 160 160 100 3.135 to 3.465 3.135 to 3.465 2.375 to 2.625 IOH = -1mA OTHER VDD25V = 2.5V 5% VDD3V = 3.3V 5% LIMITS Tamb = 0C to +70C MIN 2.0 VSS - 0.3 2.0 TYP MAX VDD + 0.3 0.8 - V V V UNIT VOL2 VOH3 VOL3 VOH3 VOL3 IOH IOH IOH IOL IOL IOL II IOZ Cin Cxtal Cout Idd3 2.375 to 2.625 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 2.375 2.625 3.135 3.465 3.135 3.465 2.375 2.625 3.135 3.465 3.135 3.465 3.465 3.465 IOL = 1mA IOH = -1mA IOL = 1mA IOH = -1mA IOL= 1mA VOUT = 1.0V VOUT = 2.375V VOUT = 1.0V VOUT = 3.135V VOUT = 1.0V VOUT = 3.135V VOUT = 1.2V VOUT = 0.3V VOUT = 1.95V VOUT = 0.4V VOUT = 1.95V VOUT = 0.4V VOUT = Vdd or GND - 2.0 - 2.4 - -27 - -29 - -33 - 27 - 29 - 30 - - IO = 0 - 0.4 - 0.4 - 0.55 - -27 - -23 - -33 - 30 - 27 - 38 5 10 5 V V V V V mA mA mA mA mA mA A A pF pF pF mA mA A mA mA A All static inputs to VDD or GND All static inputs to VDD or GND NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section. 1999 Mar 01 8 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 AC CHARACTERISTICS VDD3V = 3.3V 5%; VDDAPIC = VDD25V = 2.5V 5%; fcrystal = 14.31818 MHz CPU CLOCK OUTPUTS, CPU(0-3) (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW CPUCLK period CPUCLK HIGH time CPUCLK LOW time CPUCLK rise time CPUCLK fall time CPUCLK cycle-cycle jitter Output Duty Cycle CPUCLK pin-pin skew 45 7.5 1.87 1.67 0.4 0.4 MAX 8.0 n/a n/a 1.6 1.6 250 55 175 45 LIMITS Tamb = 0C to +70C 100MHz MODE MIN 10.0 3.0 2.8 0.4 0.4 MAX 10.5 n/a n/a 1.6 1.6 250 55 175 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0-1) (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW CPUDIV2 CLK period CPUDIV2 CLK HIGH time CPUDIV2 CLK LOW time CPUDIV2 CLK rise time CPUDIV2 CLK fall time CPUDIV2 CLK cycle-cycle jitter CPUDIV2 CLK Duty Cycle CPUDIV2 CLK pin-pin skew 45 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 250 55 175 45 LIMITS Tamb = 0C to +70C 100MHz MODE MIN 20.0 7.5 7.3 0.4 0.4 MAX 21.0 n/a n/a 1.6 1.6 250 55 175 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES PCI CLOCK OUTPUTS, PCI(0-7) (LUMP CAPACITANCE TEST LOAD = 30pF) SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW PCICLK period PCICLK HIGH time PCICLK LOW time PCICLK rise time PCICLK fall time PCICLK cycle-cycle jitter PCICLK Duty Cycle PCICLK pin-pin skew 45 30.0 12.0 12.0 0.5 0.5 MAX n/a n/a n/a 2.0 2.0 500 55 500 45 LIMITS Tamb = 0C to +70C 100MHz MODE MIN 30.0 12.0 12.0 0.5 0.5 MAX n/a n/a n/a 2.0 2.0 500 55 500 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES 1999 Mar 01 9 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 APIC(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW IOAPIC CLK period IOAPIC CLK HIGH time IOAPIC CLK LOW time IOAPIC CLK rise time IOAPIC CLK fall time IOAPIC CLK cycle-cycle jitter IOAPIC CLK Duty Cycle IOAPIC CLK pin-pin skew 45 60.0 25.5 25.3 0.4 0.4 MAX 64.0 n/a n/a 1.6 1.6 500 55 250 45 LIMITS Tamb = 0C to +70C 100MHz MODE MIN 60.0 25.5 25.3 0.4 0.4 MAX 64.0 n/a n/a 1.6 1.6 500 55 250 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES 3V66 CLOCK OUTPUT, 3V66 (0-3) (LUMP CAPACITANCE TEST LOAD = 30 pF) SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW 3V66 CLK period 3V66 CLK HIGH time 3V66 CLK LOW time 3V66 CLK rise time 3V66 CLK fall time 3V66 CLK cycle-cycle jitter 3V66 CLK Duty Cycle 3V66 CLK pin-pin skew 45 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 500 55 250 45 LIMITS Tamb = 0C to +70C 100MHz MODE MIN 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 500 55 250 ns ns ns ns ns ps % ps 1 2 2, 9, 4 5, 10 6, 10 8 8 UNIT NOTES 48MHZ(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL f fD THRISE (tR) THFALL (tF) DUTY CYCLE (tD) TJITTER PARAMETER Frequency, Actual Deviation from 48MHz Output rise edge rate Output fall edge rate Duty Cycle 133MHz CLK cycle-cycle jitter MIN MAX 500 THSTB (fST) Frequency stabilization from Power-up (cold start) NOTES: 1. See Figure 3 for measure points. MIN TEST CONDITIONS NOTES Determined by PLL divider ratio (48.008 - 48)/48 1 1 45 100MHz MAX 500 3 ms ps LIMITS Tamb = 0C to +70C MIN 48.008 +167 4 4 55 MAX MHz ppm ns ns % UNIT 1999 Mar 01 10 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 AC CHARACTERISTICS (Continued) TEST CONDITIONS SYMBOL PARAMETER CPUCLK to 3V66 CLK, CPU leads 3V66 CLK to PCICLK, 3V66 leads CPUCLK to IOAPIC, CPU leads PCICLK to CPUCLK, CPU leads CPUDIV2 to CPUCLK, CPUDIV2 leads IOAPICCLK to CPUCLK, IOAPIC leads 3V66 CLK to CPUCLK, 3V66 leads Measurement loads (lumped) CPU@30pF, 3V66@30pF 3V66@30pF, PCI@30pF CPU@20pF, IOAPIC@20pF PCI@30pF CPU@30pF CPUDIV2@20pF CPU@30pF IOAPIC@20pF CPU@30pF 3V66@30pF CPU@30pF Measure points CPU@1.25V, 3V66@1.5V 3V66@1.5V, PCI@1.5V 3CPU@1.25V, IOAPIC@1.25V PCI@1.5V CPU@1.25V CPUDIV2@ CPU@1.25V IOAPIC@20pF CPU@1.25V 3V66@1.5V CPU@1.25V LIMITS Tamb = 0C to +70C MIN 0.0 1.5 1.5 5.8 1.6 3.7 1.7 TYP MAX 1.5 3.5 4.0 ns ns ns ns ns ns ns 1 1 1 UNIT NOTES THPOFFSET THPOFFSET THPOFFSET NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks. 3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133.MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100MHz. 4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100MHz. 5. THKH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs as shown in Figure 4. 6. THKL is measured at 0.4V for all outputs as shown in Figure 4. 7. The time is specified from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1mA) JEDEC specification. 9. The average period over any 1 s period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Output (see Figure 3 for measure points). PCK2010 SPREAD SPECTRUM FUNCTION TABLE SPREAD# pin 34 SEL133/100# pin 28 SEL1 pin 33 SEL0 pin 32 Intel CK133 Function Intel CK133 48MHz PLL Philips PCK2010 Function Philips PCK2010 48MHz PLL 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 1 (inactive) 0 (100MHz) 0 (100MHz) 0 (100MHz) 0 (100MHz) 1 (133MHz) 1 (133MHz) 1 (133MHz) 1 (133MHz) 0 (100MHz) 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 3-State to High Impedance (Reserved) 100MHz, Down Spread - 0.5% 100MHz, Down Spread - 0.5% Test Mode (Reserved) 133Mhz, Down Spread - 0.5% 133Mhz, Down Spread - 0.5% 3-State to High Impedance Inactive (Reserved) Inactive Active Active (Reserved) Inactive Active Inactive 3-State to High Impedance 100MHz, Center Spread 0.5% 100MHz, Down Spread - 0.5% 100MHz, Down Spread - 0.5% Test Mode 133MHz, Center Spread 0.5% 133MHz, Down Spread - 0.5% 133MHz, Down Spread - 0.5% 3-State to High Impedance Inactive Active Inactive Active Active Active Inactive Active Inactive 1999 Mar 01 11 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 0 (100MHz) 0 (100MHz) 0 (100MHz) 1 (133MHz) 1 (133MHz) 1 (133MHz) 1 (133MHz) 0 1 1 0 0 1 1 1 0 1 0 1 0 1 (Reserved) 100MHz, No Spread Spectrum 100MHz, No Spread Spectrum Test Mode (Reserved) 133MHz, No Spread Spectrum 133MHz, No Spread Spectrum (Reserved) Inactive Active Active (Reserved) Inactive Active 100MHz, No Center Spread 0.5% 100MHz, No Spread Spectrum 100MHz, No Down Spread - 0.5% Test Mode 133MHz, No Center Spread 0.5% 133MHz, No Spread Spectrum 133MHz, No Down Spread - 0.5% Active Inactive Active Active Active Inactive Active AC WAVEFORMS VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3 VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load. VDDQ2 CPUCLK @133MHz 1.25V VSS CPUCLK @ 133MHz 1.25V VDDQ2 VSS VDDQ3 3v66 @66MHz 1.5V VSS CPU leads 3V66 THPOFFSET THPOFFSET CPUCLK leads IOAPIC IOAPIC @ 16.6MHz 1.25V VDDQ2 VSS SW00354 SW00357 Figure 1. CPUCLK to 3V66 offset Figure 3. CPU to IOAPIC offset VDDQ3 3V66 @ 66MHz 1.5V VSS 2.5V CLOCKING INTERFACE 2.0 1.25 0.4 THKP DUTY CYCLE THKH VDDQ3 PCICLK @ 33MHz THKL 1.5V VSS TPKH THPOFFSET 3V66 leads PCICLK 3.3V CLOCKING INTERFACE (TTL) 2.4 1.5 0.4 TRISE TFALL TPKP SW00356 Figure 2. 3V66 to PCI offset TPKL TRISE TFALL SW00242 Figure 4. 2.5V/3.3V clock waveforms 1999 Mar 01 12 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 VI COMPONENT MEASUREMENT POINTS 2.5VOLT MEASURE POINTS SEL133/100, SEL1, SEL0 GND VM VOH = 2.0V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS VOL = 0.4V VSS tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS outputs enabled VY tPZL VM VX COMPONENT MEASUREMENT POINTS 3.3VOLT MEASURE POINTS VOH = 2.4V VOL = 0.4V VSS VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V SYSTEM MEASUREMENT POINTS tPZH VM SW00243 outputs disabled outputs enabled Figure 5. Component versus system measure points Figure 6. 3-State enable and disable times SW00454 1999 Mar 01 13 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 S1 VDD 2 CL 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 SW00238 Figure 7. Load circuitry for switching times PWRDWN CPUCLK (INTERNAL) PCICLK (INTERNAL) PWRDWN CPUCLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO USB (48MHz) Figure 8. Power Management 1999 Mar 01 14 A A A A SW00244 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 1999 Mar 01 15 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04955 Philips Semiconductors yyyy mmm dd 16 |
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